Welcome to phyLS’s documentation!

Contents

• Introduction
• Installation
• Change Log
  • Next release
  • v2.0 (August 03, 2023)
  • v1.0 (December 20, 2022)
• Examples
  • All commands
  • Synthesis of EPFL benchmarks
• Acknowledgments

Reference

• Load
• Read
• Write into file formats
  • Write into AIGER files
  • Write into BENCH files
  • Write into BLIF files
  • Write into structural Verilog files
  • Write into DIMACS files (CNF)
  • Write into DOT files (Graphviz)
• Balance
• Create_graph
• Reduction
• Refactor
• Resub
• Resyn
• Rewrite
• Lut_mapping
• Lutmap
• Techmap
• Cec
• Sim